Genetic learning based fault tolerant models for digital systems

This work proposes two models that make use of a genetic algorithm (GA) based technique that learns the structural description of the circuit under study, in order to give it an on line fault tolerant cover. This framework helps in fault detection as well as fault correction. As the circuit operates, its input/output sequences are used to learn the structural configuration of the hardware. Once the structure is evolved, multiple versions of the same are evolved in order to increase the reliability of the system. The evolution of multiple versions is a time consuming process and may not provide complete fault coverage. In order to overcome this drawback, a redistribution algorithm that uses only a few versions, and distributes the available redundancy in an effective manner is proposed. This helps in providing up to 100% single as well as multiple component fault coverage. As part of the fault detection phase, the input/output pairs are constantly monitored for possible faults. When a fault is detected, the faulty version is replaced with a fault free version to provide correction. This helps in increasing the mean time to failure of the system. The number of versions needed for correction is also minimised. For a two-dimensional array configuration, for single component fault coverage, it is found that the number of versions to be generated ranges from just two to a maximum of the array dimensionality, with the evolution process itself being done only once. For multiple fault coverage, the number of versions goes to a maximum of nCr, where n is the array dimensionality and r is the number of multiple faults for which coverage is required. With the number of versions getting reduced because of the redistribution that is done, and the versions being evolved off-line, the overhead in terms of the system downtime and the reconfiguration time are minimised. This leads to an increase in the mean time to repair. These factors contribute to the overall improvement in reliability and availability of the system. The efficacy of the proposed techniques is studied using simulations. Hardware implementation is carried out as a proof of concept.