An efficient hardware architecture for detection of vowel-like regions in speech signal

Vowel-like regions (VLRs) in a speech signal include vowel, semivowel and diphthong sound units. In the existing VLRs detection methods, front-end speech parameterization have been done by complex algorithms. Those approaches require more hardware and hence delay the process. To address this issue, a simple and robust signal processing approach and it's hardware architecture is proposed for discriminating VLRs in the speech signal. In the proposed approach, non-local slope difference (NSD) at each time instant is computed by processing the speech signal through a single pole filter. The NSD is then averaged over an analysis frame and non-linearly mapped using negative exponential to reduce the fluctuations present in the input speech signal. The non-linearly mapped averaged NSD (NL-ANSD) is used as the front-end feature for discriminating VLRs. The NL-ANSD exhibits significantly sharp transition at the starting and ending points of the VLRs. The regions wherein the proposed feature exhibits significant transition and attains lower magnitude for a considerable duration of time are hypothesized as the VLRs. The proposed approach is very simple and requires significantly less hardware when compared with the existing zero-frequency filtering (ZFF) based methods. On the other hand, the proposed approach outperforms the existing ZFF based approaches for the task of detecting VLRs in clean as well as noisy speech signals. The hardware architecture of the proposed approach is verified by implementing it on the Nexys video Artix − 7(XC7A200T − 1SBG484C) field-programmable gate array (FPGA) trainer board for multimedia applications using Xilinx system generator-2016.2.