On-chip integrated power management MPPT controller utilizing cell-level architecture for PV solar system

• An on-chip integrated circuit for cell level architecture is presented.
• Higher efficiency, faster tracking speed, and smaller size are obtained.
• Higher power is extracted under shaded condition.
• 2 W PV cell is controlled using integrated system with high efficiency of 93%.
• A comparison between the proposed system and existing IC systems is also presented.

An on chip integrated power management circuit with maximum power point tracking (PM-MPPT) control is proposed in this paper in order to achieve high efficiency Photovoltaic (PV) system. The proposed PM-MMPT circuit mitigates partial shading issues which exist in PV systems by utilizing cell-level distributed MPPT architecture, where each cell has its own MPPT circuit, in order for each cell to produce its own maximum power without affecting other cells or being affected by other cells. The proposed PM-MPPT circuit consists of two different parts. The first part is a high-efficiency synchronous power converter stage. The second part is an analog ripple correlation control (RCC) MPPT control circuit which provides faster and efficient MPP tracking, has less circuit complexity and low power consumption. HSPICE simulation model of the proposed PM-MPPT circuit is developed with a solar cell that has 0.5 V open circuit voltage and 6 A short circuit current. Simulation results show that the proposed PM-MPPT circuit rapidly tracks the MPP with a tracking efficiency larger than 99% over a wide range of irradiation levels and 92% system power conversion efficiency at a 2 W power level. The detailed analog design of the power stage and the RCC MPPT circuits are presented and discussed in the paper based on 0.35 μm CMOS technology. In addition, the PM-MMPT IC layout is presented and discussed. To validate the proposed technique and design, a comparison between the results of the proposed circuit and other reported techniques from the literature is provided. It is shown that the proposed circuit and system are able to operate with the lowest input voltage and the highest output power compared with other reported techniques. Moreover, the proposed design has the smallest size under 2 W power level.