Experimental Demonstration of an Operand Routing Network Prototype Employing Clock Control and Data Synchronization Scheme

We have previously proposed a clock distribution and data synchronization scheme to address a problem of jitter accumulated in Large Scale SFQ circuits such as Reconfigurable Data Paths processor (RDP). The RDP is divided into several stages clocked separately by an external jitter free system clock and FIFO buffers and clock controllers between the stages are used to synchronize data. In this paper we present architecture and experimental results of an RDP prototype that employed Operand Routing Network (ORN) and clock control and data synchronization scheme designed for ISTECSRL 10 kA/cm2 advanced process. The circuit consisted of the ORN with 3 data inputs and maximum connection length equal to 1, three 8-bit input and six 10-bit output dual FIFO buffers, a 3-bit controller, a ladder type high frequency clock signal generator and six 8-bit output shift registers. Total it employed 6536 Josephson junctions and required a bias current of 0.74 A. The prototype was successfully tested at the frequencies up to 48 GHz.