کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
390516 661264 2011 14 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر هوش مصنوعی
پیش نمایش صفحه اول مقاله
A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders
چکیده انگلیسی

A new hardware-friendly mathematical method for realizing low-complexity universal Adder cells as well as its efficient hardware implementations is proposed in this paper. This method can be used in binary logic, Multiple-Valued Logic (MVL) and specifically digital fuzzy systems. The proposed mathematical method can be implemented in both voltage and current modes. The voltage-mode hardware implementation is very simple and is based on input capacitors and MVL or analog inverters and buffers. In addition, the current-mode hardware implementation leads to simple and efficient structures for digital fuzzy systems. Simulations are carried out for ternary logic as well as for digital fuzzy logic with high precision by using 180 nm standard CMOS technology and at 1.8 V supply voltage. Simulation results demonstrate that the proposed designs have excellent functionality and are very suitable for implementing MVL and fuzzy arithmetic circuits.


► The proposed arithmetic method leads to efficient adders for MVL and digital fuzzy systems.
► This method is hardware-friendly.
► This method is capable of being implemented efficiently in both voltage and current modes.
► The number of inputs is arbitrary and can increase up to r+1 for a radix-r adder.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Fuzzy Sets and Systems - Volume 185, Issue 1, 15 December 2011, Pages 111–124
نویسندگان
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