A case study of parallel JPEG encoding on an FPGA

• We apply Hill & Marty corollaries by implementing heterogeneous cores running JPEG on a real FPGA platform.
• We evaluate theoretical and experimental metrics including the speedup, area, power and core efficiency.
• We explore the hardware/software tradeoff between heterogeneous and homogeneous computing architectures.

In this note we focus on the empirical results on a case study of parallel JPEG encoding on real FPGA platform, which evaluates and complements Hill & Marty’s findings. A hardware prototype is constructed on FPGA with MicroBlaze processors and JPEG hardware accelerators. Experimental results on this case study demonstrate that the Hill and Marty’s findings reinforces the hardware/software task partitioning for hybrid MPSoC architectures and also provide creditable new insights to scalable homogeneous and heterogeneous FPGA based MPSoC domains.