An accurate performance model for network-on-chip and multicomputer interconnection networks

In this paper, we present a mathematical background for a new approach for performances modeling of interconnection networks, based on analyzing the packet blocking and waiting time spent in each channel passing through all possible paths in the channel dependency graph. We have proposed a new, simple and very accurate analytical model for deterministic routing in wormhole networks, which is general in terms of the network topology and traffic distribution. An accurate calculation of the variance of the service time has been developed, which overcomes the rough approximation used, as a rule, in the existing models. The model supports two-dimensional mesh topologies, widely used in network-on-chip architectures, and multidimensional topologies, popular in multicomputer architectures. It is applicable even for irregular topologies and arbitrary application-specific traffic. Results obtained through simulation show that the model achieves a high degree of accuracy.

► We propose a new and very accurate performance model for network-on-chip and multicomputer networks.
► The model calculates the channel waiting time using a modified M/G/1M/G/1 queuing model.
► On the network level, the model calculates the service time and its variance.
► A formal mathematical approach is used to fulfill the flow-based analysis.
► The model achieved a high degree of accuracy when compared with the simulation results.