High performance NoC synthesis using analytical modeling and simulation with optimal power and minimal IC area

This paper presents an analytical modeling and simulation NoC synthesis tool for designing low-power, high performance MPSoCs. The design process employs a power and performance predictive analysis method to combine the advantages of modeling and simulation during NoC topology generation. The synthesis tool is able to accurately account for performance metrics of the target application, while simultaneously evaluating for power related constraints using a multi-objective Tabu search based method. The tool is also able to assess and alleviate dynamic effects of contention and deadlock during synthesis. The proposed design method was tested using various multimedia and networking benchmarks, where the generated topologies were found to offer improvements in power and performance when compared to existing works.