Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos

Block-based motion estimation plays a significant role in video codecs by exploiting and reducing the temporal redundancies that exist between consecutive frames in a video sequence. Adaptive Rood Pattern Search (ARPS) is one of the most popular fast motion estimation algorithms. In this paper, VLSI design for the ARPS algorithm is proposed that involves reasonably limited hardware resource without compromising the real-time speed for transmitting HD videos. To tackle the adaptive nature of the algorithm, the proposed design avoids systolic arrays and introduces novel pattern generation methodology that can tackle the adaptive nature of the algorithm. Further, the design incorporates interleaved memory organization with a well–defined sharing strategy to re-use data and ensures high throughput. Working at a frequency of 112 MHz, the present design can process 30 Full HD 1080p (1920×1080) frames using only 47.15 K gates. Hence, the proposed VLSI architecture can be incorporated in video codecs that can be suitably used in devices like camcorders, tablets and smart phones.