Modeling and Simulation of a Many-core Architecture Using SystemC

Transistor density has made possible the design of massively parallel architectures with hundreds of cores on a single chip. De- signing efficient architectures with such high number of cores is a very challenging task. Simulation of many-core architectures is now a fundamental tool for designers to explore the design space. This paper addresses the applicability of SystemC to simulate many-core architectures. We demonstrate the use of SystemC to model a system of P cores and then simulate the execution of matrix multiplication. The simulation of the model allows analyzing the results regarding the number of transfers and the number of clock cycles required to complete each transaction. A theoretical model of the algorithm execution time is used to evaluate the precision of the system-level simulator. Simulation results indicate that the simulation models are quite precise and simulation times of a few minutes are possible for systems with a hundred of cores.