A Systolic Architecture for Hopfield Neural Networks

Recently the Hopfield Neural Network (HNN) is employed as an optimization tool to solve shortest path problem in communication networks. The hardware implementation of digital Hopfield neural network is an important issue that is considered in this paper. An efficient systolic architecture is proposed for efficient implementing of digital Hopfield neural networks for solving shortest path problem on Field-Programmable-Gate-Array (FPGA) chips. The VHDL hardware description language is employed for hardware modeling of proposed systolic architecture. The results achieved from simulation and hardware synthesizing demonstrates that the proposed systolic architecture has superior performance than relevant architectures in literature for chip area utilization, convergence and maximum operating frequency.