A parallel simulated annealing algorithm based on functional feature tree modeling for 3D engineering layout design

Computation complexity and modeling complexity are primary clog in 3D engineering layout design. In this paper, a parallel simulated annealing based on multiple Markov chains is employed to deal with the computation complexity. The algorithm increases computing efficiency by allocating computation burden to networked computers. To cope with the modeling complexity, machine components and space limitation are modeled by a hierarchical, feature-based modeling method—the functional feature tree modeling method. And multiple complex design constraints can be described by the representation. In order to support whole layout design solving process, a Computer Aided Layout Design System is introduced briefly. This system not only implements the algorithm and the components representation, but also integrates some other subsystems as evaluation system, constrains editor etc. The methods are demonstrated through a real engineering application, a vehicle engine compartment layout design.