کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
5010264 | 1462203 | 2017 | 6 صفحه PDF | دانلود رایگان |
- Vertical silicon nanowire technology with a high degree of process control (short gate length of 14Â nm).
- DC and LFN characterization of such a device.
- First proof of concept of CMOS inverters based on scaled vertical silicon nanowire architecture.
- Demonstration of multi-threshold voltage platform based on multiple NW diameter devices.
A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14Â nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling.
Journal: Solid-State Electronics - Volume 130, April 2017, Pages 9-14