کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
542685 | 1450233 | 2016 | 7 صفحه PDF | دانلود رایگان |
• The work presents a pseudo deep n-well compatible with a single-well CMOS process.
• Isolation based on the pseudo deep n-well reduces noise propagation up to 3 GHz.
• The available floating NMOS shows a slight improvement in its performance.
This work describes a fully CMOS compatible methodology, which makes available a pseudo deep n-well in single-well standard CMOS process. The proposed method is based on mask manipulation to accommodate the field implant p-type region into the n-well, and does not require any additional masks or modification in the CMOS process flow. According to the experimental results, the floating NMOS made available by the methodology shows a reduction in the threshold voltage, which implies a slight improvement in its performance, when compared with its standard NMOS counterpart. It was also experimentally demonstrated up to 3 GHz, that the guard-ring field implant/pseudo deep n-well proposed structure improves substrate noise isolation when compared to the classical p+ guard-ring, with a maximum improvement above 20 dB for low frequencies and a minimum of 4 dB at 3 GHz.
Journal: Integration, the VLSI Journal - Volume 52, January 2016, Pages 122–128