Insights on trap generation and breakdown in ultra thin SiO2 and SiON dielectrics from low voltage stress-induced leakage current measurements

We review the advancements in the understanding of breakdown and trap generation that have been achieved using low voltage stress-induced leakage current as a probe of the interface states created during electrical stress of ultra thin SiO2 and SiON gate dielectrics. The technique separates the effects of bulk and interface states on the post-stress I–V characteristics; senses interface traps at both contact interfaces, identifies the regime where interface rather than bulk state generation is the rate limiting step for breakdown, is useful for determining the operative trap creation processes, and reveals the role of trap generation mechanism in driving which stress-induced defect controls breakdown.