کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
545818 | 1450556 | 2008 | 5 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Negative bias temperature instability in n-channel power VDMOSFETs
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
Negative gate bias is used in some applications for faster switching off the n-channel MOS devices. It is shown in this study that NBT stress-related instability in commercial n-channel power VDMOSFETs could be actually more serious than in corresponding p-channel devices. NBT stress is found to create equal VT shifts in both device types, whereas the subsequent positive bias annealing results in more serious overall VT instability in n-channel devices. The changes in the densities of stress-induced interface traps in two device types are equal as well, but significant amounts of NBT stress-induced border traps are only found in n-channel devices. All the results are discussed in terms of hydrogen reaction and diffusion model.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Reliability - Volume 48, Issues 8–9, August–September 2008, Pages 1313–1317
Journal: Microelectronics Reliability - Volume 48, Issues 8–9, August–September 2008, Pages 1313–1317
نویسندگان
D. Danković, I. Manić, V. Davidović, S. Djorić-Veljković, S. Golubović, N. Stojadinović,