PLL soft functional failure analysis in advanced logic product using fault based analogue simulation and soft defect localization

Soft defect localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across the device under test (DUT). This technique has proven its usefulness for quickly locating defects that are temperature, frequency, and/or voltage dependant, for example, scan logic soft fault. However, due to high sensibility at analogue circuits SDL meets great challenges. This work gives a new flow to analyze soft functional failure in advanced logic products using fault based analogue simulation and SDL. The paper will present one case study illustrating the application of analogue simulation based soft defect localization flow as an effective means to achieve fault isolation.