An analytical two dimensional subthreshold behavior model to study the nanoscale GCGS DG Si MOSFET including interfacial trap effects

In order to pursue the miniaturization process as predicted by Moor’s law and go beyond actual reached lengths, more condensed efforts should be focused not only on looking for higher mobility materials but also on improving existing topologies of nanocircuit digital devices, which are the corner stone of currently used information storage supports. Therefore, the aim of this paper is to provide a quantitative analysis about the efficiency of our proposed structure Graded Channel Gate Stack Double Gate on Si MOSFET (GCGS DG Si MOSFET) in remedying the short channel and hot carrier degradation effects. The analysis is carried out by using an analytical 2-D subthreshold behavior model consolidated with numerical simulations (SILVACO), where the proposed structure shows an improvement and immunity against the hot carriers in terms of threshold voltage and swing factor. Moreover, the developed analytical models including the device immunity effect are compared with those of the conventional DG MOSFET, where a significant enhanced performance is predicted for the case of our proposed design. Consequently, it can be reasonably claimed that the (GCGS) DG Si MOSFET structure can alleviate the short channel and hot carrier degradation effects and further improves the device reliability for the nanoelectronic digital applications.