Design and simulation of hybrid CMOS–SET circuits

Single electron devices have extremely poor driving capabilities so that direct application to practical circuits is as yet almost impossible. A new methodology to overcome this problem is to build hybrid circuits consisting of single electron transistors (SETs) and CMOS interfaces. In this work a room temperature operable hybrid CMOS–SET inverter circuit, hybrid CMOS–SET NOR gate and their Voltage Transfer Characteristics (VTCs) are proposed. The MIB compact model for SET device and BSIM4.6.1 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment. Based on the hybrid CMOS–SET inverter, other logic gates such as NAND, NOR, AND, OR, XOR and XNOR are proposed. All the circuits are verified by means of T-Spice simulation software.