Circular Gate Tunnel FET: Optimization and Noise Analysis

This paper proposes a Silicon Tunnel Field Effect Transistor (TFET) with circular gate, and optimizes the structure for better performance. Two steps of performance optimization are adopted: reduction in ambipolar current and increase in on-off current ratio. The former objective is accomplished through introduction of gate-drain underlap, and the latter through gate-source overlap. The components of gate capacitance are analyzed and reported for the optimized structure. Furthermore, the behavior of the optimized device is observed in presence of noise sources and interface traps at two frequencies: 1MHz and 10GHz. Three noise sources, namely, Flicker Noise, Diffusion Noise and Generation-Recombination Noise are considered along with Gaussian traps of maximum concentration 1014 eV-1 cm-2.