A pattern-based routing algorithm for a novel electronic system prototyping platform

A recently proposed wafer-sized active integrated circuit capable of programmably interconnecting integrated circuits deposited on its surface needs a routing tool with computation time in the order of minutes. In this paper, a first algorithm computes the shortest route in O(n), n being the number of edges between source and destination. The second algorithm performs a parallelized random search to resolve conflicting routes. Our algorithm can route high density PCB-like netlists (25% vertices occupancy) on an 80,000 vertices regular interconnection network in about 9 min, while typical density netlists (5-15%) are routed in times ranging from 0.4 to 11 s.