Digital-domain chopping technique for high-resolution PLL-based sensor interfaces

Due to their high compatibility with scaled CMOS and emerging technologies, highly-digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancelation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a digital-domain chopping technique suited for offset and 1/f-noise cancelation in applications where medium-to-high-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10 dB of SNR gain per decade of oversampling as expected from theory.