Impact of forward and reverse deep n-well biasing on the 1/f noise of 0.13 μm n-channel MOSFETs in triple well technology

To date, flicker noise (1/f  ) compact models for describing low frequency noise performance of the n-channel transistor in DNW architecture under varying secondary body bias is lacking, since the current BSIM noise model only caters for the standard MOSFET which do not have the DNW. In this work, the authors have developed a composite low frequency noise (CLFN) model capable of modeling flicker noise in the Si/SiO2Si/SiO2 region that is affected by the modulation of surface potential by the secondary body due to the formation of parasitic bipolar and pn junctions between the channel region to the secondary body. With an improvised κ parameter that improves the varying magnitudes of noise levels associated with secondary body-source voltages and high-field effects, the CLFN model is able to accurately describe the flicker noise performance of the DNW n-channel MOSFET. Observations show that during weak inversion, forward biasing the DNW increases 1/f noise by 6 dBA/Hz, whereas reverse biasing reduces 1/f noise by 5 dBA/Hz. The authors also discover that during strong inversion, there is a slower rate of increase in 1/f noise (e.g., 0.05 dBA/Hz for every 0.1 V Vnwell decrement at Vgs = 0.8 V compared to 0.9 dBA/Hz at Vgs = 0.4 V) during DNW forward biasing. Similarly, the rate of noise reduction with respect to reverse DNW body bias is also slower (0.06 dBA/Hz for every 0.1 V Vnwell increment at Vgs = 0.8 V compared to 0.4 dBA/Hz at Vgs = 0.4 V). Noise rises with the increase in gate bias Vgs, but converges at high Vgs due to the widening of the channel. The dependence of 1/f noise on Vnwell weakens during strong inversion. Therefore clustering of noise is observed at higher n-well biases.