Simulation of self-heating effects in different SOI MOS architectures

This paper discusses self-heating effects in different silicon-on-insulator architectures by 3D electro-thermal simulations. First of all, we compare different device architectures such as planar single- and double-gate transistors, as well as FinFETs. In the second part of the article, we focus on nanoscale FinFET devices and we study the dependence of self-heating on device-structure parameters such as buried oxide thickness, source/drain extension length, fin pitch and fin height. The electron transport model has been calibrated against Monte Carlo simulations at various temperatures. The results show that under stationary conditions the rise of temperature is not negligible, and self-heating severely impacts the device performance; however, its dependence on the geometrical parameters is weak.