25-nm programmable virtual source/drain MOSFETs using a twin SONOS memory structure

25-nm PVS MOSFETs using a twin SONOS memory structure have been successfully fabricated and characterized for the first time. Compared with our previous study, the gate length, the gate oxide thickness and the storage node length are scaled down to 25, 4, and 20 nm, respectively. When erased, they show a normal transistor operation with short channel effect suppressed. However, when programmed, they remain in OFF state regardless of the gate voltage. It is confirmed that PVS MOSFETs have a good feasibility for mobile applications which require both high performance and low-power consumption.