Electrical characteristic enhancement of metal–oxide–semiconductor devices by incorporating HfON buffer layer at HfTaSiON/Si interface

In this work, the electrical characteristic enhancement of HfTaSiON-gated metal–oxide–semiconductor devices with an additional HfON buffer layer was investigated. By forming a proper thickness of HfON buffer layer at HfTaSiON/Si interface, thermal stability and electrical characteristic enhancement including EOT, hysteresis, interface trap density, stress-induced leakage current and stress-induced flatband voltage shift can be achieved. X-ray photoelectron spectroscopy (XPS) demonstrates that the atomic percentage of Si–O bonds in interfacial layer is increased by introducing HfON buffer layer at HfTaSiON/Si interface. X-ray diffraction (XRD) depicts that, while deposited on the HfON buffer layer, the HfTaSiON film shows a more significant crystalline retardation characteristic.