Designing single-cycle long links in hierarchical NoCs

In this paper we evaluate the efficiency and the system costs of wire sizing and repeater insertion as methods to reduce link delays in hierarchical NoCs. We present a unified interconnect cost function that accounts for power and wiring overheads of these methods. Then, we quantify the costs of modifying long links in typical hierarchical NoCs for different target clock frequencies and technology nodes. Although long links might undergo aggressive adjustments, we find these overall costs to be low at the system level for typical cases, taking into account that there are only a few long links in most proposed hierarchical NoC architectures. A preliminary short version of this work entitled “Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip (NoCs)” was presented in the 16th Euromicro Conference on Digital System Design (DSD), 2013.