Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE

• For the first time, ECPE based analytical model of dual material junctionless surrounding gate (JLSRG) MOSFET.
• Comparative study between gate-engineered JLSRG and simple JLSRG devices to suppress short-channel effects.
• Impact of gate-engineering on quantities like threshold voltage, surface potential, Electric Field and DIBL.

In this paper, we propose a new two-dimensional (2-D) analytical model of dual material junctionless surrounding gate MOSFET (DMJLSRG MOSFET). The expressions of potential and Electric Field of the gate engineered MOSFET structure have been obtained by solving the 2-D Poisson’s equation in subthreshold regime using a parabolic potential approximation considering effective conduction path effect (ECPE). The developed potential model accurately predicts the perceivable step function in the potential profile, responsible for effective screening of the drain potential variation in order to reduce DIBL and threshold voltage roll-off. In this work, effectiveness of dual material gate engineered (DM) design for junctionless MOSFET was scrutinized by comparing the results with a single material gate junctionless surrounding gate MOSFET (SMJLSRG MOSFET) of same dimension. From the developed potential model, a simple and accurate analytical expression of threshold voltage is also derived. Results reveal that DMJLSRG devices offer superior performance as compared to SMJLSRG devices. An improvement of hot-carrier effects (HCEs) and a reduction of short-channel effects (SCEs) have been demonstrated for gate-engineered DMJLDG device over the corresponding conventional (SMJLDG) device. The proposed model can be used as a basic design guideline for gate-engineered junctionless surrounding gate MOSFETs.