کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
462605 696872 2016 9 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A high-speed AES design resistant to fault injection attacks
ترجمه فارسی عنوان
طراحی AES با سرعت بالا مقاوم در برابر حملات تزریق خطا
کلمات کلیدی
رمزنگاری؛ الگوریتم امن AES؛ تشخیص خطا ؛ پیاده سازی FPGA؛ سیستم های جاسازی شده
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
چکیده انگلیسی

To secure the Advanced Encryption Standard against physical attacks known as fault injection attacks, different countermeasures have been proposed. The AES is used in many embedded systems to provide security. It has become the default choice for security services in numerous applications. However, the natural and malicious injected faults reduce its robustness and may cause private information leakage. In this paper, we study the concurrent fault detection schemes for achieving a reliable AES implementation. We specifically propose a new fault detection scheme based on modification of the AES architecture. For this purpose, the round AES transformation is broken into two parts and a pipeline stage is inserted in between.The proposed scheme is independent of the way the S-Box and the Inv_S-Box are implemented. Hence, it can be used for both the S-Box and the Inv_S-Box using Look-Up Table and those using logic gates based on Galois Fields. Our simulation results show the fault coverage reaches 98.54% for the proposed scheme. Moreover, the proposed and the previously reported fault detection schemes have been implemented on the most recent Xilinx Virtex FPGAs. Their area overhead, the frequency and throughput have been compared and it is shown that the proposed fault detection scheme outperform the previously reported ones.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microprocessors and Microsystems - Volume 41, March 2016, Pages 47–55
نویسندگان
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