Comments on “Fast architecture for decimal digit multiplication”

This paper proposes some corrections and comments to the BCD multiplier presented in the paper “Fast architecture for decimal digit multiplication”, published in the Journal of Microprocessors and Microsystems (Volume 39, 2015, issues 4-5, pages 296-301). Some corrections are first proposed to the presented binary multiplier, while the discussion is later extended to some issues that have been found regarding the binary-to-BCD converter.