|کد مقاله||کد نشریه||سال انتشار||مقاله انگلیسی||ترجمه فارسی||نسخه تمام متن|
|4970606||1365329||2018||12 صفحه PDF||سفارش دهید||دانلود کنید|
- Cross-connection of folded architecture lowersÂ register count.
- To reduce the latency in the DTT architecture, optimal allocation of registers is performed.
- Partial Cross Split Vedic Multiplier architecture employed reduces delay rate.
- The optimal size of multiplier design reduced the number of multipliers and adders used in the complex image transformation process.
- This architecture reduces the amount of flipflop counts and latency and improves the throughput rate.
Recently, the large size data, power and real-time processing abilities are major issues in Digital Signal Processing/multimedia applications which require an adaptable architecture. The tool used for computing data decorrelation in the image processing applications refers Discrete Tchebichef Transform (DTT) which offers better performance than the DCT due to its bitstream coding capabilities. This paper proposes a novel model of Discrete Tchebichef Transform (DTT) architecture with Register Pre-allocation based Folded Architecture (RPFA) for image compression. Through the cross-connection of folded architecture, the number of register usage is reduced. A Partial Cross Split Vedic Multiplier (PCSVM) method is introduced in the proposed DTT architecture. This multiplier design involves the cross function of the Vedic multiplier with the split pattern of multiplication binary stream. The optimal design of DTT architecture yields a minimum amount of FlipFlop (FF) counts, a latency and power consumption. The proposed PCSVM achieves higher Peak Signal to Noise Ratio (PSNR), better Structural Similarity Index (SSIM), lower delay, area, power consumption, Power-Delay Product (PDP), Mean Square Error (MSE) than the existing multiplier architectures. The proposed RPF-DTT architecture achieves a significant reduction in the resource consumption than the exact and approximate DTT architectures.
Journal: Integration, the VLSI Journal - Volume 60, January 2018, Pages 13-24