Improving the subthreshold performance of junctionless transistor using spacer engineering

In this brief, an attempt has been made to improve the ultra-low power (ULP) performance of junctionless transistor (JLT) using spacer engineering. The length of gate sidewall dual-k (high-k and low-k) spacers are optimized to improve the ULP performance of JLT. Proposed device (Dual-k JLT) shows improvement in on-current (Ion) by 72.5%, drain induced barrier lowering (DIBL) by 37.8%, subthreshold swing (SS) by 6.5%, and intrinsic delay by 35.4% at supply voltage (VDD) of 0.4 V and matched off-state current (Ioff) of 10-11 A/µm in comparison to the conventional JLT. Moreover, Dual-k JLT devices show competitive ULP performance in comparison to the inversion mode (IM) underlap device. Effect of VDD scaling on ULP performance of the JLT devices has also been studied. The effect of dual-k spacer on Junctionless accumulation-mode (JAM) device is also studied and found superior values of all the performance metrics compared to Dual-k JLT and IM devices.