Simultaneous switching noise reduction by resonant clock distribution networks

• We use an analytical method to investigate and compare the SSN in resonant clocking and conventional buffer-driven clocking.
• Using analysis (which is also supported by circuit simulations) we prove the superior noise performance of resonant clocking.
• We analyze the short-circuit power dissipation in the clocked elements in both kinds of networks.
• A thorough comparison is presented between resonant and conventional clocking from short-circuit power point of view.

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.