1.2 nm capacitance equivalent thickness gate stacks on Si-passivated GaAs

Experiments to increase the specific capacitance of MOS capacitors consisting of HfO2 on a passivating interfacial layer (IL) of amorphous Si (a-Si) on GaAs are described. XPS analysis of the layers and electrical measurements on the capacitors are combined to study the evolution of the gate stack during deposition and subsequent heat treatments. It is shown that oxidation of the a-Si IL is a major factor in preventing the attainment of a scaled capacitance equivalent thickness (CET). By controlling the deposition of the layers, the gate metal and the heat treatments, a highly scaled gate stack with a CET of 1.2 nm and a leakage reduction of more than 4 orders of magnitude with respect to SiO2/Si was realized.

The formation of low-k Hf silicate in a-Si passivated gate stacks on GaAs has been identified as the limiting factor in reaching the 1 nm CET as required for the 16 nm node and beyond. By investigating the deposition conditions of 2.5 nm HfO2/1.4 nm Si/GaAs gate stacks by an extended XPS analysis, we have shown that most of the Si oxidation takes place during the ex situ heat treatments.An optimization of all the processing steps (cleaning, gate stack composition, gate stack deposition, metallization and annealing) allowed us to demonstrate an ultra-scaled gate stack on Si passivated p-GaAs with 1.2 nm CET and excellent C–V curves with negligible hysteresis and flat- band dispersion.Figure optionsDownload as PowerPoint slideHighlights
► The formation of low-k Hf silicate in a-Si passivated gate stacks is a limiting factor to reach 1 nm CET.
► The W gate metal used as an anneal cap prevent the additional oxidation of the Si and help the CET reduce by 0.6–0.7 nm.
► An optimization of all the processing steps (cleaning, gate stack composition, gate stack deposition, metallization and annealing) allowed us to reach a 1.2 nm CET.