Experimental investigation of ESD design window for fully depleted SOI N-MOSFETs

In this article, the impact in FDSOI technology, of ground plane and buried oxide (BOX) size on the robustness and on the NMOS triggering voltage (Vt1) is shown. We show experimentally that firstly thin BOX devices are more robust than thick BOX devices and secondly with a higher Vt1, thin BOX device purposes a larger range to trigger ESD network and to optimize design.

Figure optionsDownload as PowerPoint slideHighlights
► We tested silicided MOS with Transmission Line pulse tool.
► We examine the robustness of the devices and the impact of ground planes and BOX size on MOS triggering in ESD mode.
► The lower value of triggering is reached for the thinner gate oxide and for thick BOX.
► With thin BOX, the lateral coupling decreases and the gate keeps better control on channel, preventing the parasitic bipolar from triggering too earlier.