How to improve intrinsic and extrinsic reliability of vias by process optimization

A systematic study of various processes and their impact on intrinsic reliability has been performed on Cu dual damascene interconnects. The most significant improvement for intrinsic reliability is the ‘break-through’ liner. A strong impact on stressmigration (SM) was revealed using a HDP based SiN deposition on top of Cu lines. Early failures in electromigration (EM) studies are present with insufficient cleaning processes. No reliability impact was detected with different plating and slurry chemistries and liner thickness increase. Extrinsic via reliability is assessed with a special test chip comprising 3E9 via/wafer. High ohmic vias are identified before and after thermal stress. As an example, the failure rates in Cu dual damascene levels with relaxed pitch before and after cleaning optimization are discussed.