Hot-carrier degradation model for nanoscale ultra-thin body ultra-thin box SOI MOSFETs suitable for circuit simulators

• The hot-carrier degradation of nanoscale UTBB FD-SOI n-MOSFETs has been investigated under different drain and gate bias stress conditions.
• The degradation mechanisms have been identified by studying the static current-voltage characteristics measurements.
• The impact of the HC degradation on the device parameters has been expressed with semi-empirical models in terms of the stress time, channel length, drain bias and gate bias.
• Based on our analytical compact model, HC aging model is proposed enabling to predict the device degradation stressed under different bias conditions, using a unique set of few model parameters determined for each technology through measurements.

A detailed study of the hot-carrier degradation in nano-scale fully depleted ultra-thin body and buried oxide n-MOSFETs is presented. The degradation mechanisms were identified based on static current–voltage measurements. The degradation of the transistor was explained by considering generation of traps at the gate dielectric/Si interface and traps located within a tunneling distance of the interface. All stress parameters are considered describing with semi-empirical relations their impact on the transistor parameters. Based on our analytical compact model, we propose an aging hot-carrier model predicting with good accuracy the device degradation stressed under different bias conditions using a unique set of model parameters.

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