Top-down fabrication optimisation of ZnO nanowire-FET by sidewall smoothing

• The optimisation of top-down fabrication of ZnO nanowire field effect transistor by sidewall smoothing is proposed.
• Reflow of photoresist after developed smoothed off the pattern's sidewall.
• Top-down reflow resist spacer method produced Zno nanowire with reduce surface roughness.
• Smooth nanowire has good output electrical characteristics.

This paper describes the optimisation of top-down fabrication process of the ZnO-based dual nanowire field effect transistors (NWFETs) based on the spacer method. The approach uses the top-down nanowire process with reduced sidewall roughness during pattern transfer to improve the electrical characteristics. The main feature of the process involves a reflow of the photoresist performed at a temperature of 130 °C and dry oxidation of the etched silicon sidewalls. The process optimisation leads to a significant reduction of the root-mean-square (rms) roughness of the photoresist from 23.2 nm to 3.6 nm and the ZnO nanowire rms surface roughness from 11.2 nm to 5.5 nm. The ZnO-based NWFET fabricated with the resist reflow process operates in depletion mode with a threshold voltage of − 6 V, a subthreshold slope of 0.80 V/decade, an on–off current ratio of 106, a transconductance of 5.9 nS and field effect mobility of 7.7 cm2/Vs.

Schematic of the fabrication process for (a) non-reflow resist spacer method and (b) reflow resist spacer method.Figure optionsDownload as PowerPoint slide