A design automation system for CMOS analog integrated circuits using New Hybrid Shuffled Frog Leaping Algorithm

This paper presents a new computer-aided design (CAD) system for automated sizing of analog integrated circuits (ICs). A new evolutionary algorithm, called New Hybrid Shuffled Frog Leaping (NHSFL) Algorithm, is proposed to deal with the equality and inequality constraints in the problem and to deduce the device sizes optimizing the performance of the circuits. For this, a new frog leaping rule is proposed to improve the local exploration and performance of the standard SFLA. Also, to improve the convergence velocity of the algorithm, the mutation operator is used for generating new frog, instead of random mechanism. By linking MATLAB and HSPICE the system evaluates the circuit performance during electrical simulation, in the optimization loop in the MATLAB environment, to be selected as an appropriate circuit topology. To assess the system, complex and hard-to-design analog blocks with restricted design requirements are presented in 0.18 μm CMOS process technology. The simulation results obtained from the proposed system verify that the design requirements are closely satisfied, even in tough conditions. Furthermore, some comparisons are made with available methods like Genetic algorithm (GA) and Imperialist Competitive algorithm (ICA) showing that the presented algorithm offers excellent qualifications in terms of time, efficiency and robustness.