FPGA vs. ASIC for low power applications

Field Programmable Gate Array (FPGA) are becoming more and more popular and are used in many applications. However, it is well known that the performance is limited comparing to full ASIC implementation, but for many applications the speed requirements fit the ones provided already by existing FPGA circuits. Power consumption seems to be one of the most important limiting factor and so far it is in favour of Application Specific Integrated Circuits (ASIC) [Varghese Georges, Jan M. Rabaey, Low-Energy FPGA, Architecture and Design, Kluwer Academic Publishers, 2001; Tadahiro Kuroda, Power-Aware Electronics: Challenges and Opportunities, Tutorial at FTFC 2003, Paris, May 2003]. In this paper, we will present results obtained by characterizing various circuits implemented using both FPGA and ASIC technologies in order to determine the power consumption ratio and evaluate the efficiency of the power optimization techniques such as clock gating [Amara AMARA, Philippe Royannez, VHDL for Low Power, (Chapter 11), Low Power Electronics Design, Edited by Christian Piguet, CRC Press 2005; Luca Benini, Giovanni De Micheli, Dynamic Power Management, Kluwer Academic Publishers, 1998].We have started a study in order to compare the power consumption of two Intellectual Property (IP), a counter circuit and an image transform circuit. Both circuits have been implemented using FPGA Family circuits from ALTERA and Hardware Copy of the circuits which are close to the ASIC implementation. A full ASIC implementation using UMC 0.13 μm have be also characterized in terms of power.FPGA power consumption estimation flow is based on ALTERA tools (QuartusII) that provide accurate overall power consumption for a set of input stimuli, on various targets: FPGA families and Hardware Copy. ASIC power consumption estimation flow is based on Synopsys Power tools.