کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
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543457 | 1450394 | 2009 | 4 صفحه PDF | دانلود رایگان |
SiOxNy/high-κ dielectric stack will soon replace the conventional SiOxNy-based dielectric stacks in the future generations of flash memory cells. Characterizing and reducing electron traps in the high-κ layer is an important task, as the large trap density may limit the memory retention via the trap-assisted tunneling. Since the Post-deposition Annealing (PDA) has great impact on the microstructure of high-κ dielectric, it is important to understand how PDA affects the properties of electron traps, such as the trap density, energy and spatial distributions. It is demonstrated in this paper that, by using a recently developed two-pulse C–V measurement technique, the energy and spatial distributions of electron traps throughout the SiO2/high-κ stack can be characterized, and PDA temperatures have different impacts on traps at different energy levels and spatial locations.
Journal: Microelectronic Engineering - Volume 86, Issues 7–9, July–September 2009, Pages 1834–1837