Design of a compact reversible fault tolerant division circuit

In this paper, we propose an n-bit reversible fault tolerant binary division circuit, where n is the number of bits of dividend and divisor. We present a new algorithm for division operation with the optimum time complexity in the design of dividers. The proposed division method consists of four steps: Firstly, it considers floating-point data and rounding. Secondly, it performs correctly rounded division. Thirdly, it performs correct rounding from one sided approximations. Finally, it calculates the result of the division operation. The proposed design of the divider circuit shows that it is composed of reversible fault tolerant multiplexers, parallel-in–parallel out (PIPO) left shift registers, D-Latch, rounding and normalization registers and parallel adder. The proposed divisor register and the parallel adder have the minimum quantum cost with respect to the existing ones. Fredkin gates and Feynman double gates are also used to form the divider circuit. Finally, we present an algorithm to construct a compact n-bit reversible fault tolerant binary division circuit. In this paper, a new algorithm has also been proposed to reduce the number of steps required for performing division operation. Our circuit performs better than the existing approaches considering all the efficiency parameters of reversible logic design which includes number of gates, constant inputs, garbage outputs, quantum cost and delay of the circuit, e.g., for a 256-bit binary division circuit, the proposed reversible fault tolerant binary division circuit improves 27.75% on the number of gates, 0.03% on garbage outputs, 11.04% on quantum cost, 8.94% on constant inputs and 23.50% on delay with respect to the best known existing divider circuit. We also simulate the proposed n-bit reversible fault tolerant binary division circuit using Microwind DSCH 3 which shows the correctness of the circuit.