Energy efficient design of CNFET-based multi-digit ternary adders

This paper proposes a new technique to implement multi-digit ternary ripple-carry adders in Carbon-nanotube field effect transistor (CNFET) Technology. The proposed multi-digit adder uses efficient half-adders to generate Half-Sum (HS) and Half-Carry (HC). These half-adder outputs (instead of main inputs) are used to compute carry-out at each digit-adder stage using a delay optimized carry generator. The half-sum and carry-out are then used to compute final sum at each digit-adder stage with the help of a sum generator and low-power encoders. Employing delay optimized carry generator along with low-power encoder results in energy efficient multi-digit ternary adder design. Existing and the proposed multi-digit adders of varied operand sizes are implemented in HSPICE. Simulation results show that the proposed multi-digit adder designs result in up to 52% reduction in average power consumption and 58% reduction in Power-Delay Product (PDP), when compared to other multi-digit adders in the literature.