The hysteresis-free negative capacitance field effect transistors using non-linear poly capacitance

• A gate structure design for non-hysteresis NCFET is proposed.
• Optimizations to achieve the low SS and hysteresis-free transfer are elaborated.
• Gate-to-source/drain overlap and channel length scaling are investigated.
• Interface trap states and temperature impact are considered.

A gate structure design for negative capacitance field effect transistors (NCFETs) is proposed. The hysteresis loop in current–voltage performances is eliminated by the nonlinear C–V dependence of polysilicon in the gate dielectrics. Design considerations and optimizations to achieve the low SS and hysteresis-free transfer were elaborated. The effects of gate-to-source/drain overlap, channel length scaling, interface trap states and temperature impact on SS are also investigated.