Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates

A key challenge in the engineering of Ge MOSFETs is to develop a proper Ge surface passivation technique prior to high-k dielectric deposition to obtain low interface state density and high carrier mobility. In this work, we optimise a thin, epitaxially grown, Si layer for this purpose. HfO2 is used as the high-k dielectric. With CV and TEM analysis, it is shown that the Si thickness must be controlled within a few monolayers to obtain a high-quality, defect free Ge - HfO2 interfacial layer. Ge deep sub-micron n- and p-FET devices fabricated with this technique yield promising device characteristics.