Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates

The effect of negative bias stress on p-FETs is compared for oxide vs. oxynitride gate dielectric, and for (110) vs. (100) surface orientation. Nitrogen causes increased interface state generation near the conduction band edge and reduced defect generation at mid-gap. For oxynitride grown on (110) surface only slight difference is seen compared to (100). The hole trapping contribution to the Vt shift is greater at room temperature compared to 125 °C.