Multiple gate devices: advantages and challenges

As device scaling is entering the sub-25nm range, multiple gate device architectures are needed to fulfill the ITRS requirements, since they offer a greatly improved electrostatic control of the channel. However, practical realization of multiple gate devices face with technological issues, mainly linked to the use of very thin films or very narrow active areas. On the other hand, these architectures are very likely to allow the performance improvement trend down to the sub-10nm regime and can offer new circuit design opportunities.