Effects of single grain boundary and random interface traps on electrical variations of sub-30 nm polysilicon nanowire structures

• We simulate the macaroni structure with grain boundary and interface traps.
• The macaroni structures can reduce grain boundary trap number and effect.
• The macaroni structures have additional interface traps due to the dielectric filler.
• Interface traps should be reduced in the macaroni devices for further scaling.

Effects of single grain boundary (SGB) and random interface traps (RITs) on the electrical characteristics of the macaroni structure in sub-30 nm poly-silicon (poly-Si) channel devices are analyzed using 3D simulation. The macaroni structure can mitigate the adverse effects of SGB on the electrical variations compared to the conventional structure. However, when RITs are considered at the interface between the dielectric filler and the poly-Si channel, the macaroni structures show relatively larger variations due to RITs at the inherent interface, compared with the conventional devices. Thus the reduction of interface traps in the macaroni devices is critical for sub-30 nm poly-Si device applications.

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