Assembly technology development and failure analysis for three-dimensional integrated circuit integration with ultra-thin chip stacking

• This study presents a process for wafer handling and robust assembly for thin chip stacking.
• A pre-molding technology is used to achieve extra-thin chip thickness down to 10 μm.
• Testing vehicle is fabricated to demonstrate the possibility of proposed approach.
• A simulation methodology is adopted to find the stress-induced failure of vehicles.
• Effects of underfill flexibility and die thickness of proposed framework are considered.

This study presents a process for wafer handling and robust assembly, which is a novel pre-molding technology applied to assembled stacked modules prior to chip thinning. These steps aim to overcome severe challenges of achieving extra-thin thickness as low as 10 μm for chip stacking in 3D-IC module, such as mechanical damage that appears during chip grinding. A packaging vehicle is fabricated to demonstrate the feasibility of the proposed approach. Analysis results show that underfill flexibility can relieve expansion of the produced stress to establish a 3D simulation model. The top layer of the outermost microjoint has the most serious reliability concern under a load of temperature change. Moreover, failure estimation and mechanical reliability are also performed via 3D nonlinear finite element analysis.

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