Multiprocessor SoPC-Core for FAT volume computation

This paper presents the design, co-simulation and implementation of a Soft-core for the autonomous reading of a file stored into IDE devices formatted with FAT16 File Data System. This application illustrates a novel core architecture that embeds multiple customized tiny microprocessors and standard interfaces into the core. The reconfigurable nature of the FPGA implementation allows easy modifications of the microprocessors and peripheral hardware to cover other control applications. Emphasis is placed on presenting how the co-design and co-simulation of the processors, additional hardware, buses and communications has been possible with the developed specific Virtual Environment.